Image processing requires a great amount of data movement. This data, in addition to being moved between memories and processors, must be manipulated and processed quickly. As systems become more and more sophisticated, the need for speed of operation continually increases. This requirement translates into the need for ever increasing band width or data transfer capability.
Coupled with the data movement and manipulation capability of imaging systems is the need for specialized memory to handle data transfers (pixels) to the video screen or to another output device. Thus, it has become typical to establish a VRAM (video random access memory) with enough memory capacity to hold data pixels on a one-for-one basis with the video screen. This VRAM has certain operating characteristics which allow for efficient data storage and transfer to the screen.
In an imaging system it is necessary to store images which are not to be presented to the screen but which are subject to the performance thereon of manipulations. Because DRAM (dynamic random access memory) is typically more economical and often faster than VRAM, it is desirable to process the off-screen images in a DRAM as opposed to a VRAM. This then argues for having two memory types, a VRAM for those images to be displayed, and a DRAM for storing the remainder of the images.
A problem is presented when trying to use more than one memory type in that the programmer must keep track of the timing and control, and much information must be passed to the different memory controllers to efficiently process the images. Also, because the memory capacities of each memory type are typically different, different address sizes are necessary and different control timing would apply to each memory type.
Thus, it is desirable to arrange a processing system with a single memory controller to process information to and from memories having different characteristics, such as memory size and cycle times, and even different addressing capability.
When attempting to use a single memory controller for two imaging memories, the problem of address space utilization must be resolved, together with the problem of making the controller transparent to the system programmer. The transparency is a particularly difficult problem since many parameters must be variable if a single controller is to handle two or more different memories. One requirement for any memory system is that the system be capable of handling the memory such that there is a continuity of memory address locations from one memory to the other without gaps between the memories. This is difficult to achieve when it is realized that memories having different addressable locations also must consequently be addressed using a different number of address bits.
A further problem is presented in that when two memories are used, the question arises as to how large each memory is to be. To say this another way, the question is where the split between the memories is to occur. Often it happens that it is desirable to increase the addressable space of one or the other of the memories, and when contiguous addressing is utilized this becomes a serious problem.
Thus, there is needed in the art a single memory controller which is capable of handling the addressing and control functions for a plurality of memory types having diverse operating characteristics.